1. Field of the Invention
This invention relates to electronic clocking circuits. More particularly, this invention relates to a method and apparatus for generating a clock signal having a frequency equal to an oscillator frequency divided by a fraction.
2. The Prior Art
Portable electronic devices, such as laptop computers, commonly share data with peripheral devices and other computers. One way of sharing data is through a cable linking two devices. This is cumbersome and sometimes impossible. The Infrared Data Association (IRDA) sets standards for the use of infrared serial data as a wireless means for communication. The initial IRDA standard is based on a standard personal computer serial port. An additional IRDA standard includes a 1.152 megabit per second and a 4 megabit per second mode to the interface. In effecting the IRDA standard, it is preferable to implement all of the timing standards with a single system clock, such as a 32 MHz clock. However, existing technology cannot generate clock signals having all of the frequencies corresponding to the IRDA standards by dividing a signal input from a single 32 MHz clock, because 32 MHz cannot be evenly divided by the frequencies corresponding to the IRDA standards.
Common serial port data transmission speeds are multiples of 9600 bits per second. A clock frequency of 3.6864 MHz is typically used as the primary frequency for the data transmission. The data rate is determined by using a clock circuit, having a frequency equal to the primary frequency, and a divider circuit. Commonly, a multiple of the primary clock frequency is used as a sampling clock to account for phase, jitter and frequency variations between devices.
Frequency and jitter tolerance is small for an IRDA 4 megabit per second communication interface. Therefore, a sampling frequency which is an exact multiple of the bit rate must be used. In order to have at least four samples per bit time, the minimum clock frequency for a 4 megabit per second system is 32 MHz.
The IRDA 1.152 megabit per second standard uses a non-return to zero encoding within a 2 kilobyte (or less) frame length. Zero-insertion techniques ensure that a detectable pulse is transmitted at least every five bit times. This makes it possible to create a receiver circuit using a 32 MHz sampling clock since the zero-insertion ensures that re-synchronization takes place periodically. However, transmitting based on a 32 MHz clock is not possible because a cumulative bit error will occur over the frame length and violate the IRDA specification.
Given that the IRDA four megabit interface requires very tight tolerance on the clock circuit, using a 32 MHz clock would be desirable so as to use the lowest possible operating frequency, reduce switching currents and use a single synchronous clock design.
Several existing single-clock approaches exist. However they have the disadvantage of requiring a high speed system clock (e.g., a 48 MHz, or above, clock), which can lead to problems with electromagnetic compatibility and transmission effects. Furthermore, existing single-clock methods have the disadvantage of relying on generating a non-zero cumulative bit error that depends on frame length, which could become intolerable as frame length is expanded.